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Chapter 1: About This MegaCore Function
Performance and Resource Utilization
f For information about how to apply the Speed setting, refer to volume 1 of the
Quartus II Handbook .
Table 1–7 shows the recommended device family speed grades for the Arria V,
Cyclone V, and Stratix V device families.
1–11
Table 1–7. Recommended Device Family Speed Grades for 28-nm Devices
(1)
Rate
1.25 Gbaud
2.5
Gbaud
3.125 Gbaud
5.0
Gbaud
Device
Family
Arria V (GX,
GT, SX, ST)
Arria V GZ
Stratix V
Cyclone V
(GX, GT (5) ,
SX, ST)
Mode
1x
2x
4x
1x
2x
4x
1x
2x
4x
1x
2x
4x
f MAX
1x,
2x
4x
31.25 MHz
62.5
MHz
C4, -5, C6
C4, -5, C6
C4, -5, C6
-3, -4
-3, -4
-3, -4
C1, -2, -3, -4
C1, -2, -3, -4
C1, -2, -3, -4
C6, -7, C8
C6, -7
C6, -7, C8
62.50 MHz
125
MHz
C4, -5, C6
C4, -5, C6
C4, -5
-3, -4
-3, -4
-3, -4
C1, -2, -3, -4
C1, -2, -3, -4
C1, -2, -3, -4
C6, -7, C8
C6, -7
C6, -7
78.125 MHz
156.25 MHz
C4, -5, C6
C4, -5, C6
C4 (2)
-3, -4
-3, -4
-3, -4
C1, -2, -3, -4
C1, -2, -3, -4
C1, -2, -3, -4
C6, -7, C8
C6, -7
(3)
125
MHz
250
MHz
C4 (2)
C4, -5
(3)
-3
-3, -4
-3
C1, -2, -3
C1, -2, -3, -4
C1, -2, -3 (4)
C7 (6)
-7 (7)
(3)
Notes to Table 1–7 :
(1) In this table, the entry -n indicates that both the industrial speed grade In and the commercial speed grade Cn are supported for this device
family, RapidIO mode, and baud rate.
(2) Some simple Arria V 1× variations with lane speed of 5.0 Gbaud, and some simple Arria V 4× variations with lane speeds of 3.125 Gbaud, such
as physical-layer-only variations,may meet timing in -5 speed grade devices, after following the Timing Advisor’s recommendations.
(3) Not supported for this device family.
(4) Altera recommends that for designs that include a 4× 5.0 Gbaud RapidIO IP core variation and that target a -3 speed grade Stratix V device, you
use multiple seeds in the Quartus II Design Space Explorer to find the optimal Fitter settings to meet the timing constraints. Following the Timing
Advisor's recommendations, including optimizing for speed and using LogicLock regions may be necessary to meet timing, especially for more
complex variations implemented in the largest devices.
(5) Only the -7 speed grade is available for Cyclone V GT devices.
(6) The RapidIO IP core supports 1× 5.0 Gbaud variations that target the Cyclone V device family in speed grade C7 Cyclone V GT devices only. The
RapidIO parameter editor does not warn you of this fact. You can generate a 1× 5.0 Gbaud variation that targets a Cyclone V GX variation, for
example, but when you attempt to add the extra constraints required for the RapidIO IP core, as discussed in “Specifying Constraints” on
page 2–8 , the Quartus II software Analysis and Synthesis tool fails.
(7) The RapidIO IP core supports 2x 5.0 Gbaud variations that target the Cyclone V device family in Cyclone V GT devices only. The RapidIO
parameter editor does not warn you of this fact. You can generate a 2× 5.0 Gbaud variation that targets a Cyclone V GX variation, for example,
but when you attempt to add the extra constraints required for the RapidIO IP core, as discussed in “Specifying Constraints” on page 2–8 , the
Quartus II software Analysis and Synthesis tool fails.
May 2013
Altera Corporation
RapidIO MegaCore Function
User Guide
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